This invention relates generally to voltage level conversion buffers for integrated circuit components, and more particularly to a buffer circuit which converts a logic signal at a first voltage level to a logic signal at a second different voltage level.
As it is known in the art, as integrated circuit (IC) fabrication technology has advanced, the size of transistors has been reduced allowing more transistors to fit in a given IC area. In particular, one type of transistor commonly used is so called metal-oxide-semiconductor field-effect transistors (i.e., MOSFET). A MOSFET generally includes a source and a drain each coupled to an n-type (or p-type) region having a p-type (or n-type) channel between the two regions and a gate coupled to a dielectric layer used to isolate the gate from the channel. A voltage applied to the gate induces an electric field across the gate dielectric layer and modulates the free-carrier concentration in the channel region. MOSFETs are generally small and easy to fabricate, and significant improvements in switching speed and power consumption can be made if complementary-symmetry MOSFETs (i.e., CMOS devices; both NMOS and PMOS devices) are used.
One problem with a given IC having more transistors is an increase in the amount of power required by the circuit since each transistor will require switching current when it changes from an "on" state to an "off" state and when it changes from an "off" state to an "on" state. The resulting increase in the amount of power required can lead to higher component packaging costs, overall computer system costs, larger computer systems to accommodate higher air flow due to a related increase in the amount of heat to be dissipated due to the increase in power, and the inability to use the components in battery powered computer systems.
One technique used to reduce power consumption is to reduce the supply voltage provided to the transistors in the IC. Additionally, as the transistors become smaller, a reduced supply voltage may also be required to lower the electric fields across the transistor terminals which can cause various reliability problems.
However, despite the reduction in supply voltage it is generally desirable to provide transistors which are capable of conducting a maximum current flow equal to the maximum current flow through transistors using a higher supply voltage such that transistors using a reduced supply voltage level will have comparable switching times to transistors using a higher supply voltage level. In order to accomplish this, it is generally necessary to decrease the thickness of the gate dielectric layer and channel length of the transistor.
One problem associated with thinning the gate dielectric layer is that the potential for dielectric breakdown increases. When a transistor is on, the electric field between the gate and the channel area is related to the gate to source voltage drop, Vgs, divided by the thickness of the gate dielectric layer, Tdi. (Often the gate dielectric is silicon-dioxide and the thickness of the gate dielectric is designated Tox.) As Tdi is reduced, if the value of Vgs does not change, the value of the electric field increases which increases the potential for dielectric breakdown. When Vgs reaches a certain level which is safely above the operating range of the supply voltage and specific to the process technology used to produce the device, the electric field reaches a level termed the "critical electric field". At the critical electric field level, the gate dielectric will irreparably break down and permanently change from an insulator to a conductor (i.e., the transistor behaves as a resistive short). To prevent dielectric breakdown Vgs is generally kept less than or equal to the supply voltage. Thus, the asserted input signal voltage level provided by components using higher supply voltages, Vdd, cannot be directly applied to gates of transistors which must operate at a reduced supply voltage, Vddr.
One technique used to protect a component using a reduced supply voltage, Vddr, from input signals from a component using a higher supply voltage, Vdd, is shown in FIG. 1. A component 10 is shown coupled to an input terminal 12 of a component 14. Component 10 uses a supply voltage Vdd while component 14 uses a reduced supply voltage Vddr. Input terminal 12 is shown coupled to buffer circuit 16 which includes an NMOS transistor 18 having a drain 18d, a gate 18g, and a source 18s. The drain 18d is connected to input terminal 12, the gate 18g is connected to Vddr, and the source 18s is coupled to logic element 20. Logic element 20 is shown to include an NMOS transistor 22 and a PMOS transistor 24 connected in such a way as to provide an inverter. The source 18s of the NMOS transistor 18 is connected to the gates 22g, 24g of NMOS transistor 22 and PMOS transistor 24, respectively.
A transistor is on, and thus, capable of conducting current, when Vgs is greater than Vt. Since the gate 18g of transistor 18 is connected to Vddr, transistor 18 will conduct current until the voltage Vs at the source 18s plus Vt equals Vddr (i.e., Vgs=Vt). Thus, Vs at source 18s is limited to Vddr minus Vt when the asserted signal voltage level is greater than Vddr-Vt at input terminal 12.
One problem with the buffer circuit 16 of FIG. 1 is the development of a cross-current between the PMOS transistor 24 and NMOS transistor 22 due to the limitation on Vs at the source 18s. NMOS transistor 22 will be fully conducting when the gate to source voltage drop, Vgs, is equal to Vddr, and PMOS transistor 24 will be fully off when .vertline.Vgs.vertline. is less than .vertline.Vt.vertline.. Since the maximum value of Vs at source 18s is less than Vddr, NMOS transistor 22 will not be fully conducting and PMOS transistor 24 will not be fully off which causes a cross-current from PMOS transistor 24 to NMOS transistor 22 when an asserted input signal is applied to input terminal 12. This results in a DC current component through inverter 20, and thus, a standby power requirement in component 14, hereinafter referred to as a standby current.
As the number of logic elements having a cross-current increases, the aggregate standby current may be higher than a maximum allowable standby current and may cause significant standby power consumption. This type of component may not be readily usable in a battery powered system.
A technique used to reduce the cross-current discussed above is shown in FIG. 2 where the buffer circuit 16 of FIG. 1 is shown with the addition of a PMOS transistor 26 having a gate 26g, a drain 26d, and a source 26s. The output of inverter 20 is shown connected to gate 26g, while source 26s is connected to Vddr and drain 26d is connected to the output of buffer circuit 16 and input of inverter 20. PMOS transistor 26 is one technique used to increase the voltage level provided to gates 22g, 24g of inverter 20 when the input signal applied to input terminal 12 is asserted.
As mentioned above, when an asserted input signal is applied to input terminal 12, initially, the PMOS transistor 24 will not be fully off and the NMOS transistor 22g will not be fully on. However, the output of the inverter will be approximately a low output signal. The arrangement of FIG. 2 provides this low output signal to the gate 26g of PMOS transistor 26 which turns transistor 26 on and allows current to flow from source 26s to drain 26d such that the voltage level at drain 26d is increased to Vddr provided that the asserted voltage level applied to input terminal 12 is greater than or equal to Vddr-Vt which will be discussed more fully below. Raising the input voltage level of inverter 20 to Vddr prevents the cross-current discussed above in reference to the circuit of FIG. 1.
One problem with this technique is the possibility of a back-drive current to input terminal 12 when the voltage level of an asserted input signal applied to input terminal 12 is less than Vddr-Vt. If component 14 is used in a system where the maximum voltage level of an asserted input signal is less than Vddr-Vt, or if the range of values for an asserted input signal voltage level includes voltage levels of less than Vddr-Vt, a back-drive current may be generated from PMOS transistor 26 through transistor 18 to input terminal 12. If the input signal voltage level at input terminal 12 is less than Vddr-Vt and as described above, the voltage level of the gates 22g, 24g is driven toward Vddr, the transistor 18 will begin conducting current from source 18s to drain 18d, thus, producing a back-drive current to input terminal 12.
This back-drive of current will prevent PMOS transistor 26 from pulling up the inverter 20 input to Vddr, and thus, will not eliminate the cross-current discussed in reference to the circuit of FIG. 1. Further, this back-drive current may violate very small limits placed on component input pad leakage.